Not Applicable.
This invention relates to networks and more particularly, to a bridging and switching methodology, architecture, and protocol for bridging a plurality of networks and a shared core system with interface adapters, coupled via a unique multiple bus architecture and protocol, and bus management.
Existing networks include analog (e.g., voice, composite video, etc.), and video, and can be coupled any of numerous ways including electrically and optically, and can be direct physically coupled or wireless broadcast.
Numerous products exist to permit switching across and among a plurality of similar type individual networks. One class of products are bus adapters. Bus adapters permit switching between different bus architectures. For instance, given a Nubus in the Apple Macintosh architecture and an Sbus in the Sun Spark Station architecture, the two buses could be connected together to a bus adapter that converted both the data architecture from either the Nubus or the Sbus to the other and the physical signal level on each bus. Switching across networks may also be accomplished through conventional communication protocols. Ethernet, FDDI, TCP/IP, SCSI, and the RS-232-C serial interface can perform the function of connecting disparate systems. Although these protocols are often slow and complex, they""re well understood, standardized, and well documented. Protocol converters permit a hardwired interface between different protocol interface architectures, such as Ethernet to serial.
Difficulties arise in attempting to integrate dissimilar types of network computers, data, voice, airwave broadcast, cable systems (having very high bandwidth capacity), telephone long lines, fiber optics, lease lines, etc.
A standard was achieved defining a framework from which individual designers could create their own individual solutions to implement and build from and onto an agreed upon basic specification for Asynchronous Transfer Mode (ATM) technology. By adhering to a predefined nucleus of selected common passing criteria, dissimilar data architecture and protocol systems are allowed to independently communicate along a common pathway.
Publication of Asynchronous Transfer Mode technology literature is plentiful, and is incorporated herein by reference, including the following:
ATM Forum, xe2x80x9cUser-to-Network Interface (UNI) Specificationxe2x80x9d, Version 3.0 (UNI Spec.).
ATM Forum, xe2x80x9cLAN Emulation (LANE) Specificationxe2x80x9d, Version 1.0 Case et al., xe2x80x9cSimple Network Management Protocol (SNMP)xe2x80x9d, 1990 May (RFC 1157).
Draft Recommendation 1.150, B-ISDN ATM Functional Characteristics, CCITT SG XVIII, Report R34, June 1990.
C. A. Sunshine, ed., Computer Network Architectures and Protocols, (Plenum, N.Y.).
Stassinopoulos et al., xe2x80x9cATM Adaptation Layer Protocols for Signallingxe2x80x9d, Computer Networks ISDN Systems, 23 (4) (1992), pp. 287-304.
Pirat, P., xe2x80x9cSynchronization and Error Recovery in Video Terminal Adapters in an ATM Environmentxe2x80x9d, Race 1022 Workshop, Paris, October 1989, CNET.
Fuhrmann et al., xe2x80x9cBurst and Cell Level Models for ATM Buffersxe2x80x9d, IBM Research Report RZ 2014, August 1990.
Eckbert et al., xe2x80x9cAn Approach to Controlling Congestion in ATM Networksxe2x80x9d, U-Dacs, 3 (2) (1990), pp. 199-209.
Various forays into attempting to build an ATM compatible product have yielded patchwork solutions, incomplete in their compliance with the ATM specification. In modifying existing systems, many constraints are placed on the implementation alternatives a designer can use. Nonetheless, many creative designs have evolved to permit limited access into ATM for existing computer and other data network users. Systems of this type include ATM systems or ATM bridging systems developed by Fore Systems, Newbridge, and Cisco. Fore Systems and Newbridge specialize in ATM systems, while Cisco builds routers. In addition, companies such as NetEdge build devices that multiplex multiple Ethernet ports onto a wide area network. The disadvantage of the NetEdge system is that they mix multiple users"" data much as a router would mix the data.
In attempting to implement a real system solution to ATM compatibility and simultaneously provide a bridge between dissimilar network structures, many problems are encountered. A key one is the need for a very high bandwidth bus architecture to support very high speed communications to and from each of the attached network Interface Adapters. Numerous problems exist in the various combinations of choices for obtaining high bandwidth communication between attached input/output Interface Adapters and/or a central switch core which coordinates and manages ATM traffic, including but not limited to cell flow prioritization, bus arbitration, etc. Various problems also exist with regard to bus management. Where multiple Adapters simultaneously contend for a given bus, management of collision allocation, frequency and duration, all present problems.
In accordance with one aspect of the present invention, a system architecture is provided where multiple mutually exclusive cell buses provide for the high bandwidth parallel communication of cell data between attached interface Adapters and the switch core. In accordance with a preferred embodiment of the present invention, the switch core is comprised of a shared core comprising a shared memory (logically structured in part as a circular list), a shared processor subsystem (which handles, for example, power-up initialization, including VPI and VCI translation record index tables, on-going monitoring, management by exception, and wellness testing), and a shared bus arbitration control subsystem (comprising the data in/data out queue control and the translation table mapping, and the bus master/slave apparatus and logic of the invention.
The shared core is coupled to the shared bus subsystem comprised of multiple individual cell buses, a shared processor control bus, and a shared arbitration control bus. Each attached I/O Adapter subsystem is coupled to the shared bus subsystem. The shared processor is coupled to the shared processor control bus, providing control signals thereupon for initialization and subsequent communication with and control of attached ones of the I/O adapters, such as to set up data structures (e.g., registers, translation tables, configuration data, etc.). The core processor also sets up data structures in the shared core, such as registers, flags, translation tables, configuration data, and indexed mappings logically stacked (push/pull), providing for establishment of priority and non-priority listings (data structures to support the listing) for each independent cell bus, farther comprising bus access allocation and regulation of Interface Adapter Access thereto. The Core Processor Subsystem also sets up data structures of like kind in the shared memory.
In a similar manner, the Terminal Interface Subsystem is set up by the Core Processor Subsystem.
The Core Processor subsystem can also provide ongoing monitoring of other subsystems of the shared core and attached I/O adapters, including wellness monitoring of processes, attachment status of I/O adapters, etc.
In accordance with another aspect of the present invention, the I/O Adapter is comprised of two subsystems: a common (shared) interface subsystem and a specific physical interface subsystem. The common logic interface subsystem interfaces to the shared bus subsystem to provide for bidirectional communication between the I/O Adapter and the Shared Core. As part of initialization, or subsequent reconfiguration, the shared processor can establish a shared bus selection for an I/O Adapter. Alternatively, an external switch can be provided to allow for manually determining which one of the multiple shared buses the I/O Adapter will be attached to for communication purposes. This attachment is a logical attachment. The I/O Adapter can couple to one or all independent cell buses, but be logically deactivated except as to the selected one. Upon detection by the shared core of a problem, bus arbitration and management circuitry in the shared bus can override and provide communication via a separate one of the individual cell buses. Thus, another novel and beneficial feature of the present invention is to provide for fault tolerant and redundant capabilities.
Another novel aspect of the present invention conforms to the full address mapping space specification of the ATM.UNI specification, without expenditure of huge amounts of wasted memory, provided by direct address space mapping.
Another novel feature of the present invention is provided in the combination of the apparatus and methodology of stripping the header off the cell data associating it with the shared memory pointer, translating, queuing, and reoutputting cell data from a common shared memory storage subsystem representing data from a plurality of non-associated networks, which can be totally dissimilar, but are homogenized by the use of the shared core for complete I/O type flexibility.
The management of the multiple cell buses provides another beneficial feature of the present invention. In the illustrated embodiment, each cell bus is comprised of a uni-directional transmit bus and a uni-directional receive bus. Alternative embodiments can provide for a single cell bus to be used bidirectionally in a time shared manner. Communication on each cell bus is controlled and managed by a token management subsystem comprising master and slave bus arbitration subsystems. In a preferred embodiment, the master is within the switch core, and the slaves are within the interface adapters.
In a fully populated bridge system, there can be multiple I/O Adapters contending for access to the same cell bus at the same time. In accordance with one embodiment, the system provides for prioritization of predefined individual I/O Adapters to receive priority access to the associated selected cell bus for that I/O Adapter. There may be multiple priority I/O Adapters and multiple non-priority I/O Adapters coupled to the cell buses, all associated with the same selected cell bus, all vying for access at the same time. In this case, priority and fairness must be provided. In accordance with one aspect of the present invention, the token management subsystem provides for the establishment and management of a priority token list and a non-priority token list for each of the individual cell buses. Each of these token lists is comprised of a storage area of a bus arbitration memory in the shared core, where, for example, in the illustrated embodiment, each of the three cell buses has two lists. The system and methodology for fairly managing the multiple priority and non-priority token lists for each of the cell buses is another beneficial feature provided by the present invention.
Another area of benefit is the data flow management on the I/O Adapter, in the common interface subsystem; and in the shared core, the data flow management (cell management) and queue control on the shared core system which provide for fair allocation on the cell buses for the I/O Adapters, and certain techniques used therein.
It is thus an object of the present invention to provide:
VPI/VCI Address Space Mapping
Cell Routing
Header Translation
Header/Cell Processing
Queuing
Homogenizing Bridge/Blends
Cell Bus Management
Token Management
Parallel Independent High/Low Priority Token Lists set-up and management
Data Flow (cell) Management
Queue control
Dual/Leaky Bucket Flow control of shared memory output onto cell bus.
A Shared Switch Core Architecture
A Multiple Cell Bus Architecture
These and other aspects and attributes of the present invention will be discussed with reference to the following drawings and accompanying specification.